Self-checking error checker for kappa-out-of-nu coded data

ABSTRACT

A SERIES OF SELF-CHECKING ERROR CHECKING CIRCUITS ARE DISCLOSED FOR CHECKING K-OUT-OF-N CODED DATA LINES. THE N LINES ARE BROKEN INTO TWO, PREFERABLY EQUAL, GROUPS. A LOGIC EQUATION IS DERIVED FOR EACH GROUP OF LINES WHEREBY, WITH ANY K-OUT-OF-N CODED DATA SIGNALS APPLIED TO THE INPUT, AT LEAST TWO COMPLEMENTARY OUTPUT SIGNALS ARE PRODUCED. ANY ERROR APPEARING IN THE RECEIVED CODE WILL BE INDICATED AS SUCH BY NON-COMPLEMENTARY OUTPUTS FROM   THE CHECKER IN THE OUTPUT OF THE CHECKER. MALFUNCTIONS OR FAILURES IN THE CHECKING CIRCUIT ARE CHECKED BY CERTAIN LEGITIMATE CODE SIGNALS WHICH SIMILARLY CAUSE AN ERROR REPRESENTATION IN NON-COMPLEMENTARY OUTPUTS AT THE OUTPUT OF THE CHECKER.

Jan. 26, 1971 w c, (3 T R ETAL 3,559,168

I SELF-CHECKING ERROR CHECKER FOR k-OUT-OF-CODED DATA Filed July 25,1968 6 Sheets-Sheet z FIG. 2

AND-OR FIG. 2B

OR-AND zz X5 0/8 4 v A 3 If X1 HQ 4 OR OR OR OR I A A 3 on k 21) k z1 bcLCz 6 Sheei s-Sheet 3 w. c. CARTER ET AL SELF-CHECKING ERROR CHECKERFOR k -OUT-OF-n CODED DATA Filed July 25," 1968 E v f:

Ja 26,-1971' "-ARTER ETAL 3,559,168

SELF-CHECKING ERROR CHECKER FOR k-OUT-OF -n CODED DATA I Filed July 25,1968 I e Sheebs-Sheet 4 FIG. 5

. A I x 2 x X1 W A A A A OR OR OR OR OR A FIG. 6

1 n-1 i m m+.2 n i m-1 m+1 m 2 m I on 7 0R OR OR n Ym+1 m Y1 Jan. 26,1971 w, 'CARTER ETAL- 3,559,168

SELF-CHECKING ERROR CHECKER FOR k-QUT-OF-n CODED DATA Filed July 25,1968 6 Sheets-Sheet 5 Jan. 26, 1971 w c, jA ETAL v 3,559,168

SELF- CHECKING ERROR CHECKER FOR k-OUT-OF-n CODED DATA F118;! July 25',1968 e Sheets-Sheet e United States Patent O York Filed July 25, 1968,Ser. No. 747,665 Int. Cl. H03k 13/32; G08c 25/00 US. Cl. 340-1461 ClaimsABSTRACT OF THE DISCLOSURE A series of self-checking error checkingcircuits are disclosed for checking -'k-out-of-n coded data lines. The nlines are broken into two, preferably equal, groups. A logic equation isderived for each group of lines whereby, with any k-out-of-n coded datasignal applied to the input, at least two complementary output signalsare produced. Any error appearing in the received code will be indicatedas such by non-complementary outputs from the checker in the output ofthe checker. Malfunctions or failures in the checking circuit arechecked by certain legitimate code signals which similarly cause anerror representation in non-complementary outputs at the output of thechecker.

CROSS REFERENCE TO RELATED APPLICATIONS Reference is hereby made toapplication Ser. No. 747,- 522 of W. C. Carter and RR. Schneider, filedconcurrently herewith and entitled Self-Checking Error Checker forParity Coded Data and to application Ser. No. 747,- 533 of W. C. Carter,K. A. Duke, and P. R. Schneider entitled Self-Checking Error Checker forTwo-Rail Coded Data also filed concurrently herewith for a descriptionof two similar types of self-checking checkers. The self-checkingcheckers of all of these applications have certain characteristics incommon and the cross reference to these applications may be helpful fora better understanding of the principles and operation of the presentapplication. They have been filed separately as they relate to differentdata coding systems.

BACKGROUND OF INVENTION As present day electronic computers becomeevermore complex and sophisticated, the numbers of circuits haveincreased to gigantic proportions with a concurrent reduction in timefor performing a given computation. With this large increase in thetotal numbers of circuits in todays modern complex computing systems, itwill be apparent that the number of locations in which an error or faultcan occur, has been greatly multipled. Moreover, if a given faultycomponent is producing incorrect data, a great many errors or incorrectcomputations can be produced within a very short space of time until thefault is detected.

In the past many schemes have been proposed for detecting errors invarious sections of a computing system. Probably the most wide spread isthe use of parity checking wherein an extra bit or bits accompany thetransmitted data bits and are utilized to indicate the proper datacontent of a particular transmission, i.e., normally the parity bitindicates Whether an odd or even number of 1s appears in the datatransmission proper. However, for such parity checking systems, meansmust be provided for detecting and generating the proper parity bits atvarious transmission points within the computer and additional meansmust be provided for checking the 3,559,168 Patented Jan. 26, 1971 iceparity. In the past most checking systems have not themselves beencheckable during normal data processing. In other words, if the checkerfailed so as to indicate an error free condition, subsequent errorswould obviously go undetected until some other means picked up thesystem error.

With the increasingly greater load, which must be borne by the customerengineers who have the responsibility of maintaining and repairingcomputers, any relia- =ble diagnostic circuits built in a computersystem are of invaluble aid, both in terms of indicating that an erroris present in the system and wherever possible the precise location ofthe faulty hardware. In the past the provision of large amounts of errordetection circuitry has been considered prohibitive in terms of hardwarecost. However, with the vastly more complex present day computers andthe extreme difficulty in obtaining and training qualified servicepersonnel, the cost disadvantages of reliable diagnostic equipment andcircuitry built into the computer is becoming more attractive.

Further, the advent of integrated circuit technology is rapidly reducingthe cost of individual circuit blocks to the point where heretoforefinancially unfeasible hardware installed for the purpose of errordetection and correction is beginning to look more attractive.

It will be apparent from the following description of the presentinvention that the primary concern hereof is the provision of hardwarefor the detection of errors occurring Within a computing system, bothfunction circuits and checking circuits. The particular use made of theerror detection information once obtained forms no part of the presentinvention and accordingly will not be specifically spelled out. However,it will be obvious to one skilled in the art that such information couldreadily be used for either automatic repair or for merely givingindications to appropriate service personnel for diagnostic and repairpurposes.

SUMMARY OF THE INVENTION AND OBJECTS It has now been found thatself-testing error checkers may be provided for the generalized case ofk-out-of-n coded data which will produce an error indication in theevent of either an incorrect data signal or malfunction in the checkeritself. As will be understood, a k-out-of-n code means a fixed number ofbinary ls are present in any valid data group of n bits. The instanterror checker must check each and every bit in a data set as well ashave the inherent ability of checking itself while simultaneouslyprocessing the data bits.

The self-testing checking circuits proposed by the present inventionhave two primary characteristics. The checker output distinguishes thepresence of code message inputs and error message inputs, i.e., codemessage inputs produce one set of checker outputs and error messageinputs produce a completely different (disjoint) set of checker outputs.For every given failure in the checking circuit there exists at leastone code message input which tests for that given failure, i.e., giventhe failure, when the proper code message is applied the checker willproduce an output different from that produced when code messages areapplied to a correctly functioning checking circuit. The firstcharacteristic insures that the checking circuit can be used to detectthe presence of error messages. The second characteristic insures thatthe checking circuit is completely self-testing during the normalprocessing of code messages. Special mechanisms to test for the correctoperation of the checking circuitry are eliminated.

These two characteristics require that the checking circuits have morethan one output. If only one output existed, the first characteristicwould require that the output take on one value, say 1, for codemessages and the oppo- 3 site value, say 0, for error messages. But thenthe second characteristic could not be satisfied since the checkeroutput could fail in the stuck-at-l position and application of codemessages would never detect this failure. It should be noted that thisfailure also disables all future error detection ability, thus more thanone output is mandatory.

For simplicity of discussion, each checking circuit to be described indetail here will have just two outputs. These two outputs satisfy thefirst characteristic by becoming either 01 or 10 for code message inputsand either 00" or 11 for error message inputs. Given a failure in thechecking circuit, the second characteristic is satisfied by having atleast one code message test for this given failure by producing either a00 or 11 output if the failure exists. Most of the circuits will beshown in AND- OR or OR-AND configurations but it is always possible toperform commonly known transformations to change them to NAND or NORlogic.

For the generalized k-out-of-n coded data format, the data lines areessentially broken up into a number of groups in the checked embodimentto facilitate the design of the checker. A series of logical equationsare derived to provide a circuit which will test all data lines as wellas its own operation and still meet the above criteria of providing twooutputs. The following description of the invention will indicate howthe generalized logical equations are used to design a checker circuitfor a particular code having a fixed value for k and n.

It is accordingly a primary object of the present invention to providean error checking circuit which is itself testable.

It is a further object to provide such a checking circuit for use totest k-out-of-n coded data.

It is yet another object to provide such a checking circuit having atleast two different outputs when an error free condition is present.

It is a still further object to provide such a checking circuit whichproduces a readily discernible output signal whenever an error isdetected in the coded data or the checker itself is defective.

It is a further object to provide such a checking circuit constructed ofat least two logic trees wherein the final output of each tree is asingle binary function.

It is another object to provide such a checking circuit constructed ofconventional logic blocks.

It is another object to provide such a checking circuit wherein the twooutputs of the checking circuit may be defined by boolean equations fora general k-out-of-n code wherein logic circuitry may be readilyassembled and connected to the input data lines to test said lines.

The foregoing and other objects, features, and advantages of theinvention will be apparent from the following more particulardescription of preferred embodiments of the invention, as illustrated inthe accompanying drawings.

DESCRIPTION OF DRAWINGS FIG. 1 comprises a combination, logical andfunctional, block diagram of a self-checking checker for k-out-of-ncoded data illustrating the generalized form of such a checkerconstruction in accordance with the principles of the present invention.

FIG. 2A comprises a logical schematic diagram of a functional blockperforming the function of determining if k ZZ for a 4 input bit dataset.

FIG. 28 comprises a logical schematic diagram of a functional blocksimilar to FIG. 2A for solving the statement k ZZ constructed in OR-ANDlogic.

FIG. 3 comprises the initial form of a self checking checker for2-out-of-5 data sets constructed in accordance with the general formatillustrated in FIG. 1.

FIG. 4 comprises a logical schematic diagram of the 0 output from FIG. 3which has been modified according to procedures specified in the presentinvention to make it self-checking.

FIG. 5 comprises a final logical schematic diagram of a self-checkingchecker for a 2-out-of-5 coded data sets which uses the c circuitimplementation of FIG. 3 and the 0 circuit implementation of FIG. 4 withcertain redundant, unnecessary logic blocks eliminated.

FIG. 6 comprises a generalized logical schematic diagram of aself-checking checker for the case of l-out-of-n coded data sets whereinthe required logical components are illustrated in a generalizedfashion.-

FIG. 7 comprises a logical schematic diagram of a selfchecking checkerfor deriving one of the outputs C for the case of a 4-out-of-8 encodeddata set.

FIG. 8 is similar to FIG. 7 in that it comprises a logical schematicdiagram of a self-checking checker for generating the output 0 for thecase of a 4-out-of-8 coded data set.

DESCRIPTION OF THE DISCLOSED EMBODIMENTS The objects of the presentinvention are accomplished by a self-checking error checking circuit foruse with a k-out-of-n coded data. The data lines are divided into twogroups, A and B. Said checker comprises a logical circuit for obtainingthe values of c and c according to the following relationships:

(oven values of i only) i Maze/um, zit- (odd values of i only) whereink=specified number of binary ones in the code,

n=total number of bits in the code,

k =total number of ones in Group A,

k =number of ones occurring in Group B,

n =number of bits in Group A,

n =number of bits in Group B,

a is the greater of l and (kn a is the lesser of 11,, and (k+1) 2=the ORof the terms obtained when the function is evaluated between the limitsa and 0:

It is shown in the subsequent description how the above formula isevaluated to provide circuitry capable of producing c and c with thespecific values of k and n as well as specified groups, A and B, in anumber of examples. In each of these described circuits, the finaloutputs c and 0 are complementary if both the data is error free and thechecking circuit is operating properly. If not, the outputs will be thesame and, as will be described subsequently, this coincident outputindicates an error in either the data or the checking circuit.

The bit positions X X of the data message as shown in FIG. 1 are dividedinto two groups, A and B. Any division can be used provided each groupcontains at least one bit. The resulting checking circuit is generallysimpler if the groups are approximately the same size. If they areunequal, the larger group is designated A by convention. The number ofbit positions in A and B will be designated n and u respectively.

(1) n +n =n Each checker is designed so that for code messages it givesone value of its output (e.g. 10) when there is an even number of 1s inGroup A and the other value (01) when there is an odd number of 1s inGroup A. If the number of 1s in the entire message exceeds k, the outputvalue assumes one of its error values (e.g. l1). If the number of ls isless than k, it assumes the other error value (00). The number of lsactually in the A and B portions of a given message will be design zn zl(2) c1= uaze/u tzk-m (even values of i only) C Maze/m m (odd values of ionly) Here i is an index which takes on all integer values starting at11 running up to and including a i.e., i=cc 1, a +2, a 2, a 1, a Onlythe even values of i are used in selecting the terms for the sumimplementing c and only odd values of i are used for the sumimplementing The 2 represents the OR of the set of general terms of theform shown for the set of values of i indicated and the limits aredefined as:

oi is the greater of 1, (k-n a is the lesser of n,,, (k+1) A generalimplementation of these equations is shown in FIG. 1 for the case where:1 is even and a is odd. The data buss to be checked has its lines splitinto two subbusses: one with the lines specified by A and another withthe lines specified by B. Each tree circuit (e.g. 10, and 100; or 11, 21and 101; etc.) comprises the implementation of one term of the form asspecified in Equations 2 and 3. The two OR gates 201 and 202 perform theindicated summation to generate c and c Since c is formed by summing theterms for i even and 0 by summing the terms for i odd, alternate treecircuits feed gate 201 and the remaining trees feed gate 202. If a isodd, the first tree in the sequence (and alternate ones thereafter)feeds gate 202 instead of 201. Similarly, when a is even the last treecircuit ends up feeding gate 201 instead of 202.

When igt), the logical value of the term (k i) is always 1 and thecorresponding function block in FIG. 1 need not be implemented. Alsowhen (ki n the term (k 2(ki)) always assumes the logical value 0 andthus the entire term in i and corresponding tree circuit in FIG. 1 neednot be implemented.

The "greater-than-or-equal-to" networks may be implemented either asAND-OR configurations or as OR-AND configurations, which ever is mostconvenient. To implement (k zi) in an AND-OR circuit, take differentselections of i bits from the n available bit positions in A and usethem as inputs to AND gates each gate having i inputs to receive aparticular selection. These AND gates are then ORed together to form (kzi). To implement (k zi) in an OR-AND configuration take each differentselection of (n,,I-1i) bits from the n available bit positions in A anduse them as inputs to OR gates, each gate having n +1i inputs to receivea particular selection. The outputs of the OR gates are then ANDedtogether. As an example, let A={X ,X ,X ,X n =4 and i=2. FIG. 2A showsthe AND-OR implementation of (k 22). The

possible ditferent selections of two bit positions from A are shown asinputs to the 6 AND gates. These are then ORed together in the outputgate. FIG. 2B shows the OR-AND circuit which uses OR gates each havingas input one of the 4 possible selections of 3 variables from A. Notethat when i=n the circuit becomes a single AND gate and when i=1 itbecomes a single OR gate.

In certain situations, implementing c and 0 in the tree circuits asdefined by Equations 2 and 3 will not result in a self-testing circuit.This situation will occur whenevern k (or n k) and it is necessary toimplement The tree circuit implementing this term is untested by codemessages. However, whenever this situation occurs the term (k 2k+1) willalways occur in conjunction with the term (k,zk1)(k z1). The property ofhaving the checking circuit tested by code messages is achieved bymerging the tree circuits arising from these two terms by changing thegiven expression:

( i sz ..2 b2 )l to the new, equivalent expression (5) k,,2k-1A[k,zk+1)v(k z1)] The right portion of this latter expression can beimplemented in a form tested by code messages by generating the OR-ANDversion of (k 2k+l) and entering all the bits of group B into every ORgate of that implementation. Then (k 2kl) is also implement in OR ANDform. Finally the two circuits are ANDed as specified in Equation 5 (cf.the example below).

Difliculties of testability may also arise when k n/2. In these cases itis possible to derive a testable checker by following the aboveprocedure for a designing checker except k is replaced by (n-k). Afterthe design is complete the logical complement of the resulting circuitis then taken.

A specific example will be given to show how the previous generalresults can be applied to generate self-testing checking circuits for aspecific k-out-of-n code. This example is illustrative of the reductionsobtainable for any k-out-of-n code.

Example: Consider a 2-out-of-5 code with 7 The first term and the lasttwo terms reduce because the expressions with numbers less than or equalto are always true, hence are logically 1. Equation 2 specifies c to bethe OR of the terms for i even:

1=[ b2 a2 Similarly Equation 3 specifies that c is the OR of the termsfor i odd:

Following FIG. 1, these two equations are implemented as shown in FIG.3. For i=0, 3 the greater-than-orequal-to functions are implemented asOR-AND and for i=1, 2 as AND-OR. Note again that k ZO, k ZO and k 21 arenot implemented since they always have value 1.

Examining the implementation of c shows that for i=3 the previouslymentioned special case of k k+1, or k z3 in this example, occurs. TheAND gate generating k 23 can never be tested for being stuck-at-O sinceno code message has three ls in it, a necessary condition to test thisfailure. As indicated before, the form (k 2ki) (k 2i), here (k z1) (kz1), also occurs in the circuitry implementing 0 The solution to thisproblem calls for implementing Equation using the OR-AND form of k 23with B={X X fed into each of the three OR gates and then ANDing thistree circuit with k zl. The result is shown in FIG. 4.

When the implementation of 0 in FIG. 3 and the implementation of c inFIG. 4 are refined, by removing redundant gates such as ANDs feedingANDs, single input gates, etc., the final checking circuit in FIG. 5 isobtained. It is easy to show that the code messages for a 2-out-of-5code completely tests this checking circuit for the failures where anyline is stuck-at-O or stuck-at-l. In addition, many other commonlyoccurring failures are tested.

Example: Those codes where k=1 are worthy of special notice because ofthe rather unique circuits which result for a l-out-of-n code. Al-out-of-n code is used as the output of any address or instructiondecoder and a large number of other locations in any computer system.The l-out-of-n checker described below has particular utility in theseportions of the computer system. For the following description of thepresent example let the following values apply.

It is customary (though not mandatory) to make m nearly equal to 11/2 sothat the gates in the implementation of c and c have nearly equalnumbers of inputs.

The resulting self-testing checking circuit is as shown in FIG. 6. Ingeneral each y is defined as (6) y Z X,-=X V VXi- VX V X while 0 and care specified to be r A l m+l m+2 u The correctly functioning circuit inFIG. 6 has outputs as follows:

Output:

00 Error condition where all X i are 0. 10 Code message with the 1occurring in A. 01 Code message with the 1 occurring in B.

11 Error condition where more than X is 1.

Cause The circuit in FIG. 6 is self-tested as follows:

(1) Y stuck-at-l is tested by the code message with (2) Y lgigm,stuck-at-O is tested by those (It-m) code messages which have a 1 in B.

(3) Y m-l-lgisn, stuck-at-O is tested by those :22

code messages which have a l in A.

(4) c stuck-at-l (or 0 stuck-at-O) is tested by those (nm) code messageswhich have a 1 in B.

(5) c stuck-at-O (or 0 stuck-at-l) is tested by those m code messageswhich have a 1 in A.

When a Y OR gate is not being tested its output has no effect on thechecker outputs. The OR-AND implementation is only one of the many whichexist for the functions (0 0 The ORs and ANDs may both be replaced byNORs (which has some technology advantages), the inputs and connectionsremaining unchanged. The resulting circuit has all the propertiesattributed to the previous implementation.

Example: In this example a 4-out-of-8 code checker is disclosed. Thefollowing parameters are used in this example.

Data BIISX1, X2, X3, X4, X5, X6, X7, X3

Group A=X X2, 3, 4 Group B=X X 7, 8

The following logical equations are derived for the values of c and 0using the above parameters and Equations 2 and 3 defined previously. Thelogic circuits resulting from these equations for 0 and c are shown inFIGS. 7 and 8.

One real advantage in all these implementations is that they do notrequire the use of inverters to complement the X This saves in circuitcost, delay, etc. Further it avoids the problem of having untestableinverters.

While the invention has been particularly shown and described withreference to preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade therein without departing from the spirit and scope of theinvention.

What is claimed is:

1. A self-testing error checking circuit for use with k-out-of-n codeddata, said checking circuit having it input data lines, said data inputlines being divided into two groups, A and B, said checking circuitcomprising a logical circuit for producing two outputs c and 0 saidlogic circuit being specified to obtain said values c and c according tothe following relationships:

(odd values of i only) wherein n=total number of bits in the datak=specified number of ones in any correct code group k =total number ofones in Group A k =number of ones occurring in Group B n =total numberof bits in Group A n =total number of bits in Group B a is the greaterof -1, (kn

a is the lesser of n (k+1) E=the OR of the terms obtained when thefunction is evaluated between the limits a and a i=an index which takeson all integer values starting a up to and including a wherein the datainput lines are directly connected to that portion of the logiccircuitry satisfying the greater-thanor-equal-to logic function.

2. A self-testing error checking circuit as set forth in claim 1 whereinthe individual logical greater-than-orequal-t network defined as (kzi)is implemented by selectively connecting the individual data input bitlines of the data bus to a first level of AND or OR gates, the number ofpossible input groups being defined by the formulas:

for a first level AND configuration or for a first level ORconfiguration where the AND gates would have i inputs and the OR gates(n,,+li) inputs and wherein the outputs of said AND gates are ORedtogether and the outputs of said OR gates are ANDed togetherrespectively.

3. A self-testing error checking circuit as set forth in claim 2 fortesting a two-out-of-five code wherein:

Group A=X X X Group B=X X wherein the logical circuits for deriving cand 0 are specified by the following relationship:

4. A self-testing error checking circuit as set forth in claim 2 fortesting a four-out-of-eight code wherein the following parameters aredefined:

Group A=X X X X Group B:X5, X6, X7, X3 k=4 n =4 n =4 061 0 (22 4 whereinthe logical circuits for producing the outputs c and c are specified bythe following relasionships:

1 b2 a2 b2 a2 F[( aZ bZ a2 b2 5. A self-testing error checking circuitas set forth in claim 2 for testing a l-out-of-n code wherein:

Group A=X X X Group B=X X X n =m n =nm VXi-IVX VTX wherein i=1, 2 n andwherein the logical circuits for producing the terms and c are specifiedby the relat1onsh1p:

m 2 A Yj=Y1AY2A AY i:

References Cited UNITED STATES PATENTS 2,958,072 10/1960 Batley340146.1X 3,387,263 6/1968 Dosse 340-146.1X

US. Cl. X.R.

